The present invention relates to a data driver for panel display apparatuses and in particular to a driver configured to drive the data lines of flat panel display apparatuses (LCDs, OLED displays).
Many types of flat panel display apparatuses, including liquid crystal display apparatuses and organic light-emitting diode display apparatuses, have been commercialized in recent years. One of the methods for driving such display apparatuses is active matrix. Referring to FIGS. 3A to 3C, a typical configuration of an active-matrix flat panel display apparatus (liquid crystal display apparatus or organic light-emitting diode display apparatus) will be outlined. FIG. 3A is a block diagram showing the main part configuration of a flat display apparatus; FIG. 3B shows the main part configuration of a unit pixel of the display panel of a liquid crystal display apparatus; and FIG. 3C shows the main part configuration of a unit pixel of the display panel of an organic light-emitting diode display apparatus. The unit pixels of FIGS. 3B and 3C are represented by schematic equivalent circuits.
Referring to FIG. 3A, a typical active-matrix flat panel display apparatus includes a power supply circuit 940, a display controller 950, a display panel 960, a gate driver 970, and a data driver 980. In the display panel 960, unit pixels each including a pixel switch 964 and a display element 963 are arranged in a matrix. (In a color SXGA (super extended graphics array) panel, for example, 1280×3 pixel columns×1024 pixel rows are arranged.) Scan lines 961 for transmitting scan signals outputted from the gate driver 970 and data lines 962 for transmitting gray-scale voltage signals outputted from output buffers (not shown) of the data driver 980 are arranged in a grid. The gate driver 970 and the data driver 980 are controlled by the display controller 950. Clocks CLK, control signals, and the like required for these drivers are provided thereto by the display controller 950. Image data is provided to the data driver 980 in the form of digital signals. The power supply circuit 940 supplies required power to the gate driver 970 and the data driver 980. The display panel 960 includes a semiconductor substrate. In particular, most of large-screen display apparatuses use a semiconductor substrate obtained by forming pixel switches using thin-film transistors (TFTs) on an insulating substrate such as a glass substrate or plastic substrate.
The above-mentioned display apparatus displays an image by on-off controlling the pixel switches 964 using scan signals, applying gray-scale voltage signals corresponding to pieces of image data to the display elements 963 when the pixel switches 964 are turned on, and changing the luminance of the display elements 963 in accordance with the gray-scale voltage signals.
Data corresponding to one screen is rewritten in one frame period (usually, about 0.017 sec at a 60-Hz drive frequency). Specifically, pixel rows (lines) corresponding to the scan lines 961 are sequentially selected, that is, the pixel switches 964 are turned on. Gray-scale voltage signals are provided from the data lines 962 to the display elements 963 via the pixel switches 964 in a selection period. In some cases, multiple pixel rows are simultaneously selected by a single scan line or the display apparatus is driven at a frame frequency of 60 Hz or more.
Referring to FIGS. 3A and 3B, the display panel 960 of the liquid crystal display apparatus includes a semiconductor substrate, a counter substrate, and liquid crystal sealed between the opposite two substrates. The semiconductor substrate has unit pixels each including a pixel switch 964 and a display element 963 arranged in a matrix thereon. The counter substrate has a single transparent electrode 974 formed on an entire surface thereof. A display element 963 included in a unit pixel includes a pixel electrode 973, the counter substrate electrode 974, a liquid crystal capacitance 971, and an auxiliary capacitance 972. The display panel is also provided with a backlight as a light source over its back. When the pixel switches 964 are turned on (activated) by scan signals from the scan lines 961, gray-scale voltage signals from the data lines 962 are applied to the corresponding pixel electrodes 973. The potential difference between each pixel electrode 973 and the counter substrate electrode 974 changes the transmittance of light emitted by the backlight and passing through the liquid crystal. The potential difference is held in the corresponding liquid crystal capacitance 971 and auxiliary capacitance 972 for a given period of time even after the corresponding pixel switch 964 is turned off (inactivated), thereby displaying an image. Meanwhile, to prevent degradation of the liquid crystal, liquid crystal display apparatuses are driven in such a manner that the polarity (positive or negative) of the common voltage of the counter substrate electrode 974 is inverted for each pixel, usually, every one frame period (inversion drive). Typical inversion drive types include dot inversion drive, where adjacent pixels show different voltage polarities, and column inversion drive, where adjacent data lines show different voltage polarities. In dot inversion drive, gray-scale voltage signals having different voltage polarities are outputted to the data lines 962 every selection period (every data period); in column inversion drive, gray-scale voltage signals having the same voltage polarity are outputted to the data lines 962 every selection period (every data period).
Referring to FIGS. 3A and 3B, a display panel 960 of an organic light-emitting diode display apparatus includes a semiconductor substrate having unit pixels each including a pixel switch 964, an organic light-emitting diode 982, and a thin-film transistor (TFT) 981 arranged in a matrix thereon. The organic light-emitting diode 982 is composed of an organic film between two thin film electrode layers. The TFT 981 controls the current supplied to the organic light-emitting diode 982. The TFTs 981 and the organic light-emitting diodes 982 are coupled in series between power supply terminals 984 and 985 that receive different power supply voltages. The unit pixel further includes an auxiliary capacitance 983 for holding the control terminal voltage of the TFT 981. A display element 963 corresponding to the unit pixel includes the TFT 981, the organic light-emitting diode 982, the power supply terminals 984 and 985, and the auxiliary capacitance 983. When the pixel switches 964 are turned on (activated) by the scan signals from the scan lines 961, gray-scale voltage signals from the data lines 962 are applied to the control terminals of the corresponding TFTs 981. The TFTs 981 supply currents corresponding to the gray-scale voltage signals to the corresponding organic light-emitting diodes 982, which then emit light with luminance corresponding to the currents, thereby displaying an image. Even after the pixel switches 964 are turned off (inactivated), the gray-scale voltage signals applied to the control terminals of the TFTs 981 are held in the auxiliary capacitances 983 for a given period of time. Thus, the light emission is maintained. While the pixel switch 964 and the TFT 981 are composed of n-type transistors in this embodiment, they may be composed of p-channel transistors. Alternatively, the organic EL element may be coupled to the power supply terminal 984. The organic light-emitting diode display apparatus does not need to be driven by inversion drive unlike the liquid crystal display apparatus; gray-scale voltage signals corresponding to the pixels are outputted every selection period (every data period). While the organic light-emitting diode display apparatus makes an image on the basis of the gray-scale voltage signals from the data lines 962 in this embodiment, it may make an image on the basis of gray-scale current signals outputted from the data driver.
As described above, in the above-mentioned display apparatuses, data corresponding to one screen is rewritten every frame period (usually, about 0.017 sec at a 60-Hz drive frequency). Specifically, pixel rows (lines) corresponding to the scan lines are sequentially selected (that is, the pixel switches are turned on), and the data lines provide gray-scale voltage signals to the display elements via the pixel switches turned on in a selection period. One selection period refers to a period of time obtained by dividing about one frame period by the number of scan lines. The data driver outputs gray-scale voltage signals corresponding to pieces of image data to the data lines every selection period. Hereafter, a data driver configured to drive active-matrix display apparatuses will be described.
The data driver includes multiple digital-analog conversion circuits (D/A converters). Each D/A converter generates reference voltages corresponding to gray-scale characteristics by dividing γ-voltages applied externally using resistors and selects a reference voltage corresponding to received digital image data from the reference voltages. The selected reference voltage is inputted to the output buffer (output amplifier) of a voltage follower. The respective numbers of D/A converters and output buffers correspond to the number of data lines of the display panel. Gray-scale voltage signals corresponding to pieces of image data are outputted to the data lines of the display panel. Generally, data drivers comprise semiconductor driver LSIs (large scale integrated circuits). One or more driver LSIs corresponding to the number of data lines of the display panel are mounted on the display panel. The driver LSIs provide gray-scale voltage signals to the data lines of the display panel.
Display apparatuses for use in televisions or display apparatuses for personal computer have been provided with larger screens with higher resolutions in recent years. The number of data lines of the display panel has been increased accordingly. As a result, the data driver (driver LSIs) has been required to have more outputs (more pins). For example, with regard to liquid crystal televisions or the like supporting full high-definition (full HD) (height 1080×width 1920×RGB), the number of data lines is 1920×3. The data drivers (driver LSIs) are coupled to these data lines. For a data driver having 720 outputs, 8 data drivers are required; for a data driver having 960 outputs, 6 data drivers are required; and for a data driver having 1440 outputs, 4 data drivers are required. As the number of data drivers to be mounted is reduced, the number of members required to mount data drivers is reduced. As a result, cost can be reduced. However, the distance between the output pads of the data drivers (driver LSIs) is smaller than that between the data lines of the display unit of the display panel. This increases the difference between the lengths (the difference between the maximum length and the minimum length) of the leader lines in the fan-out region extending from the edge of the display unit to the pads of the driver LSIs. Thus, the difference in resistance between the leader lines is increased, which may cause unevenness in display. As a countermeasure, a method is proposed for reducing the difference in resistance between the leader lines.
FIG. 4 is a diagram schematically showing the configuration of a flat display panel. A display panel 90 shown in FIG. 4 includes a display unit 91, a scan line drive circuit 92, and data drivers (driver LSIs) 100. The data drivers 100 are composed of silicon LSIs or silicon LSIs packaged with a tape-shaped thin film (called TCP (Tape Carrier Package) or COF (Chip on Film)).
While three data drivers 100 are shown for the sake of convenience in the example shown in FIG. 4, the number of data drivers 100 varies depending on the number of data lines of the display panel and the number of outputs of one data driver 100. In a display apparatus having a large display panel, the display panel 90 is driven using multiple data drivers 100. The display panel 90 is divided into the same number of regions as the number of data drivers 100, and each region is driven by the corresponding data driver 100.
The pitch of the output terminals of one data driver 100 is smaller than the distance between the data lines installed in the display unit 91. (The driver output terminals may be the output pads of TCP or COF.)
To couple the data lines of the display unit 91 to the data drivers 100, the leader lines of the data lines are installed obliquely in the shape of sectors in a fan-out region 99 extending from the edge of the display unit 91 to the data drivers 100 in such a manner that the distance between the adjacent leader lines is reduced toward the data drivers 100.
Thus, a shorter leader line (low resistance) is coupled to the chip center of the data driver 100, and a longer leader line (high resistance) is coupled to the chip end thereof. A large difference in resistance between the leader lines makes a large difference between the data line drive waveforms (rounding, etc.) of gray-scale voltage signals outputted from the data driver 100.
For this reason, even when gray-scale voltage signals having the same gray scale are outputted, the rate of voltage write to the pixel may vary depending on the difference in rounding between the signal waveforms. This may make a difference in luminance between the display regions corresponding to the respective data lines coupled to the chip center and the chip end, causing unevenness in display.
Data drivers have been required to have more outputs than conventional 720 or fewer outputs in recent years, for example, 960 outputs or 1000 or more outputs. As the number of outputs of one data driver 100 increases, the difference in resistance between the leader lines increases, easily causing unevenness in display.
Where the scan line drive circuit 92 is composed of a gate driver (LSI), the leader lines take a shape similar to that for the data drivers 100. Where the scan line drive circuit 92 is formed as a thin film transistor circuit on the display panel 90, the leader lines coupled to the outputs thereof may have an equal length.
A method for compensating for the differences in resistance between the leader lines of the data lines (or gate lines) in the fan-out region 99 is disclosed in Japanese Unexamined Patent Application Publication No. Hei 10(1998)-153791. Japanese Unexamined Patent Application Publication No. Hei 10(1998)-153791 discloses a liquid crystal display apparatus including: multiple display-side electrodes disposed at an edge of a liquid crystal display unit, multiple terminal-side electrodes disposed at the junction of TCP, parallel lines connecting the corresponding display-side electrodes and terminal-side electrodes and extending from the terminal-side electrodes in a direction identical to the direction of the disposition of the terminal-side electrodes, radial lines extending from the parallel lines radially and reaching the display-side electrodes, and line electrodes having a small width, wherein the lengths of the parallel lines become longer as the distances between the corresponding display-side electrodes and terminal-side electrodes are shorter and wherein parts of the parallel lines in the line electrodes are formed into bent lines that each have one or more bends in accordance with the length thereof and that approximately match the resistances of the line electrodes with each other. In Japanese Unexamined Patent Application Publication No. Hei 10(1998)-153791, the shorter leader line coupled to the chip center is bent in such a manner that the resistance of the shorter leader line is matched with that of the leader line coupled to the chip end.
However, bending the leader line reduces the distance between the adjacent lines. This may easily cause shorting between the adjacent lines or a break in the bend, reducing the yield of the display panel.
Japanese Unexamined Patent Application Publication No. 2004-70317 discloses a configuration where compensation resistors are disposed at the outputs of a driver LSI so as to compensate for the differences in resistance between the leader lines. FIG. 5 is a diagram obtained by referring to FIG. 5 of Japanese Unexamined Patent Application Publication No. 2004-70317. In FIG. 5, compensation resistors 109 are disposed between output buffers 101 corresponding to the outputs of a data driver 100 and driver output terminals 102. The resistances of the compensation resistors are set such that the respective sums of these resistances and the resistances of the corresponding leader lines in a fan-out region 99 are the same.
For the compensation resistors 109 of FIG. 5, the resistances of the compensation resistors adjacent to the chip ends (outputs OUT1, OUT384 of the data driver 100) and corresponding to the longest leader lines (high resistance) in the fan-out region 99 are set to 0Ω; the resistances of the compensation resistors coupled to the chip center (outputs OUT92, OUT93 of the data driver 100) and corresponding to the shortest leader lines (low resistance) in the fan-out region 99 are set to 1069Ω; and the resistances of the other compensation resistors are set such that a compensation resistor closer to the chip center has a higher resistance.
FIG. 6 is a diagram showing a typical output configuration of a data driver (driver LSI) of a display apparatus as the related art. (FIG. 6 is drawn by the inventors.) Referring to FIG. 6, a data driver 100 includes multiple driver output terminals (pads) 102_1 to 102_4, output protective resistors 104_1 to 104_4 having ends coupled to the driver output terminals (pads) 102_1 to 102_4, output buffers 101_1 to 101_4, and multiple output switches 103_1 to 103_4 coupled between the output nodes of the output buffers 101_1 to 101_4 and the other ends of the output protective resistors 104_1 to 104_4. To simplify the description, FIG. 6 shows four output buffers 101, four driver output terminals (pads) 102, four output switches 103, and four output protective resistors 104.
The output buffers (amplifiers) 101_1 to 101_4 amplify and output image signals to be outputted to data lines 96_1 to 96_4. The output switches 103_1 to 103_4 have the function of temporarily blocking gray-scale voltage signals outputted from the output buffers 101_1 to 101_4 to the corresponding data lines in accordance with a common control signal S1. For example, the output switches 103_1 to 103_4 are temporarily turned off to change the gray-scale signals so as to prevent transition noise caused by the change of the gray-scale signals from being transmitted to the data lines. For another example, to recover the electric charge of the data line capacitance by shorting adjacent data lines in order to reduce power consumption, the output switches 103_1 to 103_4 are turned off in common to block gray-scale voltage signals outputted from the output buffers 101_1 to 101_4 to the corresponding data lines. The output protective resistors 104_1 to 104_4 are disposed in order to prevent electrostatic damage, and the resistances thereof are set to similar resistances.